For those interested in custom #hardware (circuits, not packaging):

"#Yosys is a framework for #Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. […]"

https://www.clifford.at/yosys/

This is another similar (and better known) tool:

"#Icarus Verilog is a #Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format."

https://iverilog.icarus.com/

See also:

ADMS - An automatic device model synthesizer

"#ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile C code for the API of #spice simulators. Based on transformations specified in #XML language, ADMS transforms #Verilog-#AMS* code into other target languages."

https://github.com/Qucs/ADMS

* https://en.wikipedia.org/wiki/Verilog-AMS

And, to play with the electric circuits themselves, graphically:

QUCS - Quite Universal Circuit Simulator

"#Qucs is an integrated #circuit simulator which means you are able to setup a circuit with a graphical user interface (GUI) and simulate the large-signal, small-signal and noise behaviour of the circuit. After that simulation has finished you can view the simulation results on a presentation page or window."

https://github.com/Qucs/qucs

This is a front-end fir #SPICE.