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Prior to agreement on the methods the subject matter is just irrelevant.

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PSA: I'm not a "conservative". Don't reach to me for your validation.

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aphorism 

Never demand explanation.
Never demand understanding.

networking, v6 

IPv6 is good and all but TBH I don't know how to use it in a LAN. AFAIU I'm supposed to simply generate a random subnet (collisions are very unlikely), instead of picking a range from the standard IPv4 private networks. But to do that I use what? Not `hexdump -e … < /dev/urandom` I suppose.

Imagine if there's a LaTeX debugger and you can do web-style "inspect element" debugging and visualize those hboxes....

just finished reading a book and listening to a podcast series, much needed sense of accomplishment

funny how I'd still regularly visit Fedi even when I don't want to see or talk to anyone (which is like most of the time); that's not to say I want to interact with the mainstream Fedi either, but still

software 

So Linux now requires LLVM as a build dependency?

technical nonsense 

Part of the reason why there are no built-in circular shifts is because when you need it you also need to separate the parts (shifted up and down) into two different values.

For example, write-strobes, combined with unaligned addresses, need to be rotated to the remainder of the address divided by bus width, then the two parts of the rotated strobe are applied to consecutive rows.

language 

So many insults, like *bro or creep for example, just go over my head. No idea what the speaker is ever accusing somebody else of. Or perhaps it's just an insider vocabulary with no definite meaning and only used to check or claim an affiliation.

How to use minkowsky sums in #FreeCAD to accurately scale complex objects for adjustable fit clearance. Also may work for proportional scaling for shrinkage allowance in #3dprinted lost PLA casting.

reprapltd.com/3d-printing-clea

hardware, rant 

The real reason why hardware is so obscure is not the infamous protection of "intellectual property", but more likely a profound shame, and also the fear of consumers finding out what garbage they are consuming.

If inspecting websites' front-ends wouldn't be this easy, those who make them would probably also not shut up about how innovative they are, and how they must protect their inventions, and how thoroughly they test everything, and how much trust you must put in them, you name it.

re: hardware 

In VHDL, if you leave an output(s) of a component unassigned, you must explicitly declare them as "open". While in Verilog, if you not assign any inputs of a module, it's OK, the translator will only maybe issue a warning and proceed as if nothing happened… 🤦

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hardware 

One aspect of RTL design, foreign to the software developers, is the widths and ranges:
Every signal or register may have any width, not just 8 * 2k. The indices don't always start from 0 or 1, but the start index is explicitly given. And the order of the indices may be as ascending (e.g. [0:7]) as descending (e.g. [7:0]).

Meanwhile the range limits are inclusive, so to define an empty array or bit-vector (say as a general case of the configuration) you'd have to use ranges like "descending from n - 1 to n", but Verilog may as well interpret it as 2-elenment array/bit-vector with ascending order of indices instead of 0-element array/bit-vector with descending indices… that's why VHDL distinguishes to and downto in the range.

Moreover in Verilog there are index ranges to the left and to the right of the declared identifier, it boils down to the distinction between packed and unpacked (padded for alignment) values. For example, an array logic [7:0] arrgh [0:3] can't be seen as just logic [0:31] bv or logic ar [0:31], And even if the concatenation of a signals should have the same width, the translator will still complain that width doesn't match (without specifying what the widths are BTW, good luck guessing it for yourself).

To replicate typical constructions over multiple indices, you're supposed to use the "for"-"loop", which isn't a loop of course but essentially a templating directive. This expression is very picky about the types of the index variables, the ranges, and how you use the variable in the index range. Basically it's just a parody on the for-loops in C. If the variable needs to linearly affect as the upper as the lower index of an array/bit-vector in the body, you can't do that, only in special cases you can utilize the -: and +: delimiters, if the distance between the indices is fixed.

Concatenation (of e.g. bit-vectors), doesn't have a parametric generalization, so you'd need to rewrite it "for" assigning to individual bits.

In SV there are also "genvar" + "generate" constructions used when just "for" doesn't suffice. Where to apply which is a mystery. Just another redundant syntax perhaps.

To recap: it's even easier to introduce subtle bugs in Verilog than in JS, and most hardware is probably full of it. I really don't have much respect to this language or it's authors, and nobody should write it directly, if it can't be avoided. While VHDL seems fine.

#TIL CVE-2020-8705. Intel Boot Guard prevents any unsigned boot firmware code from executing on the CPU on boot, making it impossible to modify and reflash your UEFI/BIOS. But if you enter ACPI S3 "sleep" mode, then reflash the EEPROM, finally wakeup the computer, Boot Guard is bypassed.

I wonder if you can use a microcontroller and a multiplexer to automate this exploit. Sounds like a great way to run a modded BIOS...

The Internet — a place to discuss anything but what really matters.

hardware protocols 

AXI4 bus is still kinda complicated. Today's pitfall is the unaligned access and the strobes:
Each bit indicates which octet of the data bus is valid / should be considered. If the address selects a cell of that width, then no problem, it's just a mask. But if the addressable units are smaller than the bus width, still regarding the strobe as a mask is neither intuitive nor how the existing devices are using it.
Looks like the strobe'd octets should be placed in sequence starting from given address in octets.
Then what if addressable units are larger than an octet and yet smaller than the data bus width? The specification doesn't appear to say a lot about it.

nonsense 

pop coroutines — returning to what never happened

script kidding 

ICYWW how to search for simple binary patterns without any heavy equipment: e.g.

find -type f | while read fp; do hexdump -e '1/1 "%02x "' $fp | egrep --color=always "$(echo '0b:ad:fa:ce' | sed 's/:/ ([[:xdigit:]]{2} ){,3}/g')" && echo $fp; done

Will find a pattern where the four octets are separated by at most three octets between the neighbors.

Systemd+Linux intricacies 

How else a process may discover that it's being run via systemd-run and not started directly from the shell? Provided the arguments and environment variables are the same, and tty returns a sensible /dev/pts/* (tried both, --pty and --pipe options).

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